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Description: 用verilog写的16阶串行DA算法FIR滤波器-Verilog written by 16-order FIR filter serial DA algorithm
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Size: 576512 |
Author: 代鑫 |
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Description: 使用verilog语言实现的fir滤波器,使用了内部的触发器资源,优化。-Verilog language used to achieve the fir filter, the use of internal resources of the flip-flop, and optimize.
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Size: 1024 |
Author: liang jianbing |
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Description: 一个 FIR 滤波器的 verilog 实现, 与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
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Size: 97280 |
Author: wei |
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Description: 一个不错的关于lms算法的verilog代码,算然只有两级,但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
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Size: 1024 |
Author: onion |
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Description: 基于verilog的FIR滤波器程序设计(调试过的)-verilog
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Size: 638976 |
Author: 柳澈 |
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Description: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
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Size: 350208 |
Author: rayax |
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Description: 16阶FIR VHDL程序并附带testbench,并有简单流水线设计!-16 Tap FIR vhdl code with testbench and pipelining design
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Size: 352256 |
Author: hongwan |
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Description: 本文以软件无线电为指导,提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构;然后采用模块化设计思想,将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计;最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
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Size: 201728 |
Author: jiang |
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Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
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Size: 3090432 |
Author: 胡文静 |
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Description: FIR filter verilog project
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Size: 34816 |
Author: Yoshi |
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Description: FIR抽取滤波器,抽取系数3,Verilog版本,数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
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Size: 2048 |
Author: 王刚 |
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Description: 使用verilog语言实现64阶FIR,调试可以通过-64 taps FIR with verilog
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Size: 19456 |
Author: 黄锦江 |
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Description: verilog hdl fir 48阶-verilog hdl fir
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Size: 90112 |
Author: 张兵 |
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Description: 做作业的时候用VERILOG编写的FIR滤波器程序,希望对大家有用-Homework time FIR filter with VERILOG written procedures, we want to be useful
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Size: 1024 |
Author: 龙兰飞 |
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Description: FIR filter using verilog code
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Size: 2150400 |
Author: Karama |
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Description: 实现FIR滤波,利用Verilog语言对其进行了设计
-FIR filter implementation using Verilog language design was carried out
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Size: 4126720 |
Author: 翁萍 |
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Description: low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response
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Size: 4225024 |
Author: 吴恒 |
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Description: verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
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Size: 1378304 |
Author: yuanjun |
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Description: finite impulse response LMS algorithm verilog code
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Size: 36864 |
Author: zcos123 |
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Description: 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2:串行DA fir3:并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
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Size: 2048 |
Author: |
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